This invention relates generally to processing within a computing environment, and more particularly to managing command queues in a multilevel cache hierarchy.
In computers, a cache is a component that improves performance by transparently storing data such that future requests for that data can be served faster. The data that is stored within a cache might be values that have been computed earlier or duplicates of original values that are stored elsewhere (e.g. main memory). If requested data is contained in the cache (cache hit), this request can be served by simply reading the cache, which is comparably faster. Otherwise (cache miss), the data has to be recomputed or fetched from its original storage location, which is comparably slower.
The operation of cache operations in a shared cache are controlled by a cache controller. The cache controller may include a shared pipeline that processes individual requests. A pipeline may be considered as a set of data processing elements connected in series, so that the output of one element is the input of the next one. An instruction pipeline may be used in a computing device to increase instruction throughput (the number of instructions that can be executed in a unit of time). The fundamental idea is to split the processing of a computer instruction into a series of independent steps, with storage at the end of each step. This allows the computer's control circuitry to issue instructions at the processing rate of the slowest step, which is much faster than the time needed to perform all steps at once. The term pipeline refers to the fact that each step is carrying data at once (like water), and each step is connected to the next (like the links of a pipe.)
Caches that employ a pipeline, typically is a pool of command queues that are available to process commands received from another unit or chip. These queues may be able to process several different varieties of commands and are generally loaded in a fixed rank-based ordering scheme for simplicity. In such a system, different commands may require access to different secondary resources (e.g., other chips or devices) and if these resources are unavailable the command queue is forced to wait until they are available. In some cases, the different command queues may have access to different secondary resources.